Example embodiments of the inventive concept relate to a semiconductor device, and particularly, to a complementary metal oxide semiconductor (CMOS) device having a metal gate stack structure.
Generally, a gate stack structure of a metal oxide semiconductor (MOS) device includes a gate insulating layer formed on a semiconductor substrate and a gate formed on the gate insulating layer. Conventionally, a silicon oxide layer is used as the gate insulating layer, and a polysilicon layer is used as the gate.
As the size of the MOS device is decreased, the thickness of the gate insulating layer is reduced, and a line width of the gate is also gradually reduced. It is difficult to reduce the thickness of the gate insulating layer further due to physical limitation(s), and as the thickness of the gate insulating layer is reduced, a leakage current increases. As a result depletion occurs at an interface between the polysilicon silicon layer and the gate insulating layer, and the characteristic of the MOS device is deteriorated. Also, it is difficult to reduce a threshold voltage in a MOS device in which the silicon oxide layer is used as the gate insulating layer and the polysilicon layer is used as the gate.
As such, for higher/improved performance, the material and structure of the gate insulating layer and the gate of the gate stack structure needs to be changed. Furthermore, a complementary MOS (CMOS) device includes a NMOS (N-channel MOS) device and a PMOS (P-channel MOS) device. Thus, the material and structure of the gate stack structure of each of the NMOS device and the PMOS device also need to be changed.